Non-volatile memory devices are often used in consumer electronic products such as smart phones and tablets. There are various types of non-volatile memory devices such as resistive random access memory devices (ReRAMs), magnetic random access memory devices (MRAMs) and phase-change magnetic random access memory devices (PCRAMs).
FIG. 1A shows a top view of a prior art memory cell 100 including a plurality of prior art non-volatile memory devices 102 electrically coupled to bit lines 150 (e.g. BL0, BL1, BL2, BL3) and word lines 152 (e.g. WL0, WL1, WL2, WL3). FIG. 1B shows a perspective view of one of the prior art memory devices 102 and FIG. 1C shows a cross-sectional view of one of the prior art memory devices 102 along the line A-A′. As shown in FIGS. 1A to 1C, the memory device 102 includes a top electrode 106, a bottom electrode 126 and a switching element 118 arranged between the top electrode 106 and the bottom electrode 126. For simplicity, only the top electrodes 106 are shown in FIG. 1A. The switching element 118 is normally insulating. However, upon application of a sufficiently high voltage difference between the top and bottom electrodes 106, 126, a dielectric breakdown event can occur, forming conducting filaments 166 within the switching element 118. The switching element 118 thus becomes conductive and the resistance of the switching element 118 decreases. A lower voltage difference may be applied between the top and bottom electrodes 106, 126 to break the conducting filaments 166, causing the resistance of the switching element 118 to increase. The prior art memory device 102 may be considered to be in a low resistance state (LRS) when the conducting filaments 166 are formed and in a high resistance state (HRS) when the conducting filaments 166 are broken.
Current non-volatile memory devices, such as prior art memory device 102, often suffer from plasma damage during a dry etch process carried out during fabrication of the devices. The dry etch process often causes cornering of the top electrodes and as a result, plasma damage often occur at the edges of the switching elements. Defects arising from such plasma damage can significantly limit the endurance performance of the memory devices. Further, the top and bottom electrodes of current non-volatile memory devices often have much larger dimensions than the conducting filaments formed within the switching elements. For example, a length 106l and a width 106w of the top electrode 106 of the prior art memory device 102 may both be greater than tens of nm. A length 126l and a width 126w of the bottom electrode 126 of the prior art memory device 102 may also be both greater than tens of nm. However, each conducting filament 166 formed within the switching element 118 may only be a few atoms in size or may have dimensions in the sub-nm range. Therefore, multiple conducting filaments 166 may be formed at random within the switching element 118, and there may be incomplete rupture at certain portions of the switching element 118. This may cause a huge variation in the resistance of the switching element 118 (and thus, the memory device 102) across multiple dielectric breakdown events.
It is therefore desirable to provide an improved memory device with less variability in its resistance and better endurance performance.